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Voltage Regulators
AN8049FHN
1.8-volt 3-channel step-up, step-down, and polarity inverting DC-DC converter control IC
I Overview
The AN8049FHN is a three-channel PWM DC-DC converter control IC that features low-voltage operation. This IC can form a power supply that provides two stepup outputs and one step-down or polarity inverted output with a minimal number of external components. Minimal operating supply voltage of this IC is as low as 1.8 V, so that it can operate from 2 dry-batteries.
20 5.200.10 (5.00) 19 13
3-
Unit: mm
C0 .5 0
24 R0.30 1 7
8
(0.77)
0.10 4.000.10 (1.10) (0.77) 1 24 7
Seating plane
(0 .1 5)
* Wide operating supply voltage range: 1.8 V to 14 V 20 12 * High-precision reference voltage circuit 13 (0.44) 19 0.600.10 -- VREF pin voltage: 1% 0.50 0.200.06 0.10 -- Error amplifier: 1.5% QFN024-P-0405A (Lead-free package) * Ultrathin surface mounting package for miniaturized and thinner power supplies * Supports control over a wide output frequency range: 20 kHz to 1 MHz * On/off (sequence control) pins provided for each channel for easy sequence control setup * The negative supply error amplifier supports 0-volt input. Common-mode input voltage range: - 0.1 V to VCC -1.4 V This allows the number of external components to be reduced by two resistors. * Fixed duty factor: 86% However, the duty can be adjusted to anywhere from 0% to 100% with an external resistor. * Timer latch short-circuit protection circuit (charge current: 1.1 A typical) * Low input voltage malfunction prevention circuit (U.V.L.O.) (operation start voltage: 1.67 V typical) * Standby function (active-high control input, standby mode current: 1 A maximum)
(0.44)
M
I Applications
* Electronic equipment that requires a power supply system
3.000.10
I Features
8
(1.10)
0.80 max.
0.200.10
(4.00) 4.200.10
12
Publication date: December 2001
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AN8049FHN
I Block Diagram
CTL1 VREF OSC IN-1 DT1 VCC FB1 Off
0.7 V 0.3 V
22
14
21
5
7
2
15
1.1 mA
1.26 V (Allowance: 1%)
50 k
Reference voltage supply VREF
Triangular wave generator
6
On/off control VCC 9 10 PWM1
30 k
Error amplifier 1
20 k 1.26 V 50 k
RB1 OUT1
1.26 V
VCC
1.1 mA
S.C.P. FB3
23 18 Error 16 amplifier 2
U.V.L.O. R SQ Latch
1.26 V
S.C.P. comp.
0.9 V
PWM3
50 k 50 k
13
IN+3 17 IN-3 DT3 CTL3 24 3
OUT3
VREF
1.1 mA 20 k 1.26 V
VCC PWM2
Error amplifier 3
8 11
RB2 OUT2
20 k
1.26 V
1.1 mA
VREF
50 k 1.26 V 50 k
12
30 k
19
20
GND
4
CTL2
IN-2
I Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 DT2 DT1 CTL3 CTL2 CTL1 Off VREF RB2 RB1 OUT1 OUT2 GND Description Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 OUT3 VCC OSC IN+3 IN-3 FB3 IN-2 FB2 IN-1 FB1 S.C.P. DT3 Description
2
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DT2
FB2
1
AN8049FHN
I Absolute Maximum Ratings
Parameter Supply voltage Off pin allowable application voltage Error amplifier input allowable application voltage *2 OUT1 and OUT2 pin output source current OUT3 pin output current Power dissipation *1 Operating temperature Storage temperature Symbol VCC VOFF VIN ISO(OUT) ISI(OUT) PD Topr Tstg Rating 14.2 14.2 VCC -50 +50 111 -30 to +85 -55 to +150 Unit V V V mA mA mW C C
Note) *1: Ta = 85C. For the independent IC without a heat sink. *2: When VCC is less than 6 V, VIN-1 and VIN+2 must be VCC .
I Recommended Operating Range
Parameter Off pin application voltage OUT1 and OUT2 pin output source current OUT3 pin output current Timing resistance Timing capacitance Oscillator frequency Short-circuit protection time-constant setting capacitance Output current setting resistance Symbol VOFF ISO(OUT) ISI(OUT) RT CT fOUT CSCP RB Range 0 to 14 -40 (min.) 40 (max.) 3 to 33 100 to 1 000 20 to 1 000 1 000 (min.) 750 to 15 000 Unit V mA mA kW pF kHz pF
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AN8049FHN
I Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 F, Ta = 25C
Parameter Reference voltage block Reference voltage Line regulation with input fluctuation Load regulation VREF temperature characteristics VREF pin short-circuit current U.V.L.O. block Circuit operation start voltage Error amplifier 1 block Input threshold voltage 1 Input bias current 1 High-level output voltage 1 Low-level output voltage 1 Output source current 1 Output sink current 1 VTH temperature characteristics 1 Open-loop gain 1 Error amplifier 2 block Input threshold voltage 2 Input bias current 2 High-level output voltage 2 Low-level output voltage 2 Output source current 2 Output sink current 2 VTH temperature characteristics 2 Open-loop gain 2 Error amplifier 3 block Input offset voltage Common-mode input voltage range Input bias current 3 High-level output voltage 3 Low-level output voltage 3 Output source current 3 Output sink current 3 Open-loop gain 3 VIO VICR IB3 VEH3 VEL3 ISO(FB)3 ISI(FB)3 AV3 -6 - 0.1 - 0.6 1.0 -38 0.5 - 0.3 1.2 -31 80 6 VCC - 1.4 1.4 0.2 -24 A mA dB mV V A V VTH2 IB2 VEH2 VEL2 ISO(FB)2 ISI(FB)2 VTHdT2 AV2 Ta = -30C to +85C 1.241 1.0 -38 0.5 1.26 0.1 1.2 -31 1.5 80 1.279 0.2 1.4 0.2 -24 A mA % dB V A V VTH1 IB1 VEH1 VEL1 ISO(FB)1 ISI(FB)1 VTHdT1 AV1 Ta = -30C to +85C 1.241 1.0 -38 0.5 1.26 0.1 1.2 -31 1.5 80 1.279 0.2 1.4 0.2 -24 A mA % dB V A V VUON 1.59 1.67 1.75 V VREF Line Load VRFEdT IOC IREF = - 0.1 mA VCC = 1.8 V to 14 V IREF = - 0.1 mA to -1 mA Ta = -30C to +85C 1.247 -20 1.26 2 -3 1 -10 1.273 20 V mV mV % mA Symbol Conditions Min Typ Max Unit
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I Electrical Characteristics at VCC = 2.4 V, CREF = 0.1 F, Ta = 25C (continued)
Parameter Oscillator block Oscillator frequency Frequency supply voltage characteristics Frequency temperature characteristics Output 1 block Output duty factor 1 High-level output voltage 1 Low-level output voltage 1 Output source current 1 Output sink current 1 Pull-down resistor 1 Output 2 block Output duty factor 2 High-level output voltage 2 Low-level output voltage 2 Output source current 2 Output sink current 2 Pull-down resistor 2 Output 3 block Output duty factor 3 Output saturation voltage Du3 VO(SAT) RT = 7.5 k, CT = 680 pF 80 0.8 VSCP = 0 V -1.3 86 0.9 -1.0 1.26 92 0.2 % V Du2 VOH2 VOL2 RT = 7.5 k, CT = 680 pF IO = -10 mA, RB = 1 k IO = 10 mA, RB = 1 k VO = 0.7 V, RB = 1 k 80 VCC - 1 -32 40 20 86 -27 30 92 0.2 -22 40 % V V mA mA k Du1 VOH1 VOL1 RT = 7.5 k, CT = 680 pF IO = -10 mA, RB = 1 k IO = 10 mA, RB = 1 k VO = 0.7 V, RB = 1 k 80 VCC - 1 -32 40 20 86 -27 30 92 0.2 -22 40 % V V mA mA k fOUT fDV fDT RT = 7.5 k, CT = 680 pF RT = 7.5 k, CT = 680 pF RT = 7.5 k, CT = 680 pF 170 190 1 3 210 kHz % % Symbol Conditions Min Typ Max Unit
ISO(OUT)1 VO = 0.7 V, RB = 1 k ISI(OUT)1 RO1
ISO(OUT)2 VO = 0.7 V, RB = 1 k ISI(OUT)2 RO2
Short-circuit protection circuit block Input standby voltage Input threshold voltage Input latch voltage Charge current Comparator threshold voltage On/off control block Input threshold voltage Off pin current CTL block Input threshold voltage Charge current Whole device Average consumption current Standby mode current ICC(OFF) ICC(SB)
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VSTBY VTHPC VIN ICHG VTHL
0.1 1.0 0.1 -0.7
V V V A V
VON(TH) IOFF VOFF = 5 V
0.7
1.0 35
1.3
V A
VTHCTL ICTL VCTL = 0 V RB = 9.1 k, duty = 50%
1.07 -1.3
1.26 -1.0
1.47 -0.7
V A
4.2
5.5 1
mA A 5
AN8049FHN
I Terminal Equivalent Circuits
Pin No. 1 Equivalent circuit Description DT2: Sets the channel 2 soft start time. Set the time by connecting a capacitor between this pin and ground. Note that although the channel 2 maximum on duty is set internally to 86%, the maximum on duty can be set to a value of 86% or less by inserting a resistor between this pin and ground, and can be set to a value of 86% or more by inserting a resistor between this pin and the VREF pin. DT1: Sets the channel 1 soft start time. Set the time by connecting a capacitor between this pin and ground. Note that although the channel 1 maximum on duty is set internally to 86%, the maximum on duty can be set to a value of 86% or less by inserting a resistor between this pin and ground, and can be set to a value of 86% or more by inserting a resistor between this pin and the VREF pin. CTL3: Controls the on/off state of channel 3. A delay can be provided in the power supply turn-on start time by connecting a capacitor between this pin and ground. tDLY3 = 1.26 (V) x CCTL3 (F)/1.1 (A) (s) This pin can also be used to control the on/off state with an external signal. In that case, the allowable input voltage range is from 0 V to VCC. Note that during U.V.L.O. and timer latch operation, this pin is connected to ground through a 20 k resistor. CTL2: Controls the on/off state of channel 2. A delay can be provided in the power supply turn-on start time by connecting a capacitor between this pin and ground. tDLY2 = 1.26 (V) x CCTL2 (F)/1.1 (A) (s) This pin can also be used to control the on/off state with an external signal. In that case, the allowable input voltage range is from 0 V to VCC. Note that during U.V.L.O. and timer latch operation, this pin is connected to ground through a 20 k resistor. I I/O I
7 20 15 50 k 1 50 k PWM2
2
7 22 15 50 k 2 50 k PWM1
3
VCC 1.1 A
20 k
High channel 3 operation 1.26 V is turned off.
3
4
VCC 1.1 A
I
20 k
High channel 2 operation 1.26 V is turned off.
4
6
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AN8049FHN
I Terminal Equivalent Circuits (continued)
Pin No. 5 Equivalent circuit Description CTL1: Controls the on/off state of channel 1. A delay can be provided in the power supply turn-on start time by connecting a capacitor between this pin and ground. tDLY1 = 1.26 (V) x CCTL1 (F)/1.1 (A) (s) This pin can also be used to control the on/off state with an external signal. In that case, the allowable input voltage range is from 0 V to VCC. Note that during U.V.L.O. and timer latch operation, this pin is connected to ground through a 20 k resistor. Off: Controls the on/off state. When the input is high: normal operation (VOFF > 1.2 V) When the input is low: standby mode (VOFF < 0.6 V) In standby mode, the total current consumption is held to under 1 A. VREF: Outputs the internal reference voltage. The reference voltage is 1.26 V (allowance: 1%) when VCC is 2.4 V and IREF is - 0.1 mA. Insert a capacitor of at least 0.1 F between VREF and ground for phase compensation. RB2: Connection for a resistor that sets the channel 2 output source current. Use a resistor in the range 750 to 1.5 k.
11 200 8 30 k
I/O I
VCC 1.1 A
20 k
High channel 1 operation 1.26 V is turned off.
5
6
100 k Start and stop of internal circuits.
I
6
7
VCC
O
7
8
VCC
I
9
VCC
RB1: Connection for a resistor that sets the channel 1 output source current. Use a resistor in the range 750 to 1.5 k.
I
10 200 9 30 k
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AN8049FHN
I Terminal Equivalent Circuits (continued)
Pin No. 10 9 ISO(OUT)1 10 30 k Equivalent circuit VCC Description OUT1: Push-pull output. The absolute maximum rating for the output source current is -50 mA. Connecting the external resistor to RB1 terminal allows this circuit to provide an output source current with excellent line regulation and minimal sample-to-sample variations. OUT2: Push-pull output. The absolute maximum rating for the output source current is -50 mA. Connecting the external resistor to RB2 terminal allows this circuit to provide an output source current with excellent line regulation and minimal sample-to-sample variations. GND: Ground. 12 13 OUT3: Open-collector output. The absolute maximum rating for the output current is +50 mA. I/O O
11
8
VCC
O
ISO(OUT)2 11 30 k
12
VCC 13
O
14
14
VCC: Power supply terminal. Provide the operating supply voltage in the range 1.8 V to 14 V. OSC: Connection for the capacitor and resistor that determine the oscillator frequency. Use a capacitor in the range 100 pF to 1 000 pF and a resistor in the range 3 k to 33 k. Use an oscillator frequency in the range 20 kHz to 1 MHz. IN+3: Noninverting input to the error amplifier 3. IN-3: Inverting input to the error amplifier 3.
15
VCC Latch S Q 0.2 V R 15
O
16
VCC
I
17
17 1.5 k
16 1.5 k
I
8
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AN8049FHN
I Terminal Equivalent Circuit (continued)
Pin No. 18
7
Equivalent circuit
Description FB3: Output from the error amplifier 3. This circuit can provide a source current of -31 A or a sink current of 0.5 mA (minimum).
I/O O
16 17
31 A OSC
PWM3
0.5 mA min.
18
19
14
IN-2: Inverting input to the error amplifier 2.
I
19
1.5 k 1.26 V
20
VCC 31 A OSC PWM2
19 1.26 V
FB2: Output from the error amplifier 2. This circuit can provide a source current of -31 A or a sink current of 0.5 mA (minimum).
O
0.5 mA min. 20
21
14
IN-1: Inverting input to the error amplifier 1.
I
21
1.5 k 1.26 V
22
VCC 31 A OSC PWM1
21 1.26 V
FB1: Output from the error amplifier 1. This circuit can provide a source current of -31 A or a sink current of 0.5 mA (minimum).
O
0.5 mA min. 22
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AN8049FHN
I Terminal Equivalent Circuits (continued)
Pin No. 23 Equivalent circuit
VCC 1.1 A 1.5 k
Description S.C.P.: Connection for the capacitor that sets the timer latch short-circuit protection circuit time constant. Use a capacitor with a value of 1 000 pF or higher. The charge current ICHG is 1.1 A typical.
I/O O
Latch S Q 1.26 V R Output shutoff
23
24
7 18 15 50 k 24 50 k PWM3
DT3: Sets the channel 3 soft start time. Set the time by connecting a capacitor between this pin and ground. Note that although the channel 3 maximum on duty is set internally to 86%, the maximum on duty can be set to a value of 86% or less by inserting a resistor between this pin and ground, and can be set to a value of 86% or more by inserting a resistor between this pin and the VREF pin.
I
I Usage Notes
[1] Allowable power dissipation Since the power dissipation (P) in this IC increases proportionally with the supply voltage, applications must be careful to operate so that the loss does not exceed the allowable power dissipation, PD , for the package. Reference formula: P = (VCC - VBEQ1) x ISO(OUT)1 x Du1 Power dissipation in the channel 1 output stage + (VCC - VBEQ2) x ISO(OUT)2 x Du2 Power dissipation in the channel 2 output stage + VO(SAT)3 x IOUT3 x Du3 Power dissipation in the channel 3 output stage + VCC x ICC Power dissipation between VCC and ground < PD VBEQ1 : The voltage between the base and emitter of the npn transistor Q1 ISO(OUT)1 : The OUT1 pin output source current (When RRB1 is 1 k, ISO(OUT)1 will be 38 mA, maximum.) Du1 : The output 1 duty factor VBEQ2 : The voltage between the base and emitter of the npn transistor Q2 ISO(OUT)2 : The OUT2 pin output source current (When RRB2 is 1 k, ISO(OUT)2 will be 38 mA, maximum.) Du2 : The output 2 duty factor VO(SAT)3 : The OUT3 pin saturation voltage (0.5 V maximum when OUT1 is 40 mA.) IOUT3 : The OUT3 pin current (This will be {VCC - VBEQ3 - VO(SAT)3}/RO3 .) Du3 : The output 3 duty factor ICC : The VCC pin current
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I Usage Notes (continued)
[2] Allowable VCC ripple VCC ripple due to the switching transistor being turned on and off can cause this IC's U.V.L.O. circuit, which is biased by VCC , to operate incorrectly, and can cause the S.C.P. capacitor charging operation to fail to start when the output is shorted. The figure shows the allowable range for VCC ripple. Applications should reduce VCC ripple to be within this range, either by inserting a ripple filter in the VCC line or by inserting a capacitor between the IC GND and VCC pins and locating that capacitor as close to the IC as possible. Note that the allowable range shown here is the result of testing the IC alone and that the allowable range may differ depending on the actual structure of the power supply circuit. Also note that this allowable range is a design target, and is not guaranteed by testing of all samples. Allowable VCC ripple
10M Allowable range when VCC is 3 V. 1M
Ripple frequency (Hz)
100k
Allowable range when VCC is 10 V. 10k 0 1 2 3 4 5 6 7 8
VCC ripple voltage VCC(AC) (V[p-p])
I Application Notes
[1] PD Ta curves of QFN024-P-0405A PD T a
1.200 1.075 1.000 When mounted on a 4-layer printed circuit board (50 x 50 x t0.8 mm3) Rth(j-a) = 93.0C/W When mounted on a standard printed circuit board (glass epoxy: 50 x 50 x t0.8 mm3) Rth(j-a) = 151.5C/W
Power dissipation PD (W)
0.800
0.660 0.600
0.400 0.279 0.200 Independent IC without a heat sink Rth(j-a) = 357.4C/W 0.000 0 25 50 75 85 100 125
Ambient temperature Ta (C)
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AN8049FHN
I Application Notes (continued)
[2] Main characteristics Timing capacitance Oscillator frequency
1M
95
fOSC Maximum output duty
RT = 3 k
90
Du1 , Du2 , Du3 (%)
fOUT (Hz)
RT = 3 k 100k RT = 7.5 k
Du3 Du1 , Du2
85
80
RT = 33 k 10k 10p
75 10k 100k 1M
1n
10n
CT (F)
fOSC (Hz)
fOSC Maximum output duty
95 RT = 7.5 k
fOSC Maximum output duty
95 RT = 33 k
Du2
90
90
Du3 Du1
Du1 , Du2 , Du3 (%)
85
Du1 , Du2 , Du3 (%)
1M
Du3
85
Du1 , Du2 80
80
75 10k
100k
75 10k
100k
1M
fOSC (Hz)
fOSC (Hz)
RB ISO(OUT)
0 -10 -20 VCC = 1.8 V
RB ISI(OUT)
100 90 80 70
ISO(OUT) (mA)
ISI(OUT) (mA)
-30 2.4 V -40 -50 -60 -70 -80 100 14 V 8V
60 50 40 30 20 10
VCC = 14 V
8V 1.8 V, 2.4 V 1k 10k 100k
1k
10k
100k
0 100
RB ()
RB ()
12
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AN8049FHN
I Application Notes (continued)
[3] Timing charts VCC pin voltage waveform 1.67 V Output short S.C.P. pin voltage waveform 1.26 V
CTL pin voltage waveform 1.26 V
FB
OSC
DT
0.9 V
OUT1/2 pin voltage waveform Totem pole circuit output (Step-up output)
OUT3 pin voltage waveform Open-collector output (Inverting or step-down output)
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AN8049FHN
I Application Notes (continued)
[4] Function descriptions 1. Reference voltage block This circuit is composed of a band gap circuit, and outputs a 1.26 V (typical) reference voltage that is temperature compensated to a precision of 1%. This reference voltage is stabilized when the supply voltage is 1.8 V or higher. This reference voltage is used by error amplifiers 1 and 2. 2. Triangular wave generator This circuit generates a triangular wave like a sawtooth with a peak of 0.7 V and a trough of 0.2 V using a capacitor CT (for the time constant) and resistor RT connected to the OSC pin (pin 15). The oscillator frequency can be set to an arbitrary value by selecting appropriate values for the external capacitor and resistor, CT and RT . This IC can use an oscillator frequency in the range 20 kHz to 1 MHz. The triangular wave signal is provided to the noninverting input of the PWM comparator in each channel internally to the IC. Use the formulas below for rough calculation of the oscillator frequency. 1 1 fOSC - 0.8 x (Hz) VOSCL CT x RT CT x RT x ln VOSCH
VOSCH 0.7 V
t1 Rapid charge
t2 Discharge T
VOSCL 0.2 V
Figure 1. Triangular oscillator waveform
Note, however, that the above formulas do not take the rapid charge time, overshoot, and undershoot into account. See the experimentally determined graph of the oscillator frequency vs. timing capacitance value provided in the main characteristics section. 3. Error amplifier 1 This circuit is an npn-transistor input error amplifier that detects and amplifies the DC-DC converter output voltage, and inputs that signal to a PWM comparator. The 1.26 V internal reference voltage is applied to the noninverting input. Arbitrary gain and phase compensation can be set up by inserting a resistor and capacitor in series between the FB1 pin (pin 22) and the IN-1 pin (pin 21). The output voltage VOUT1 can be set using the circuit shown in the figure. 4. Error amplifier 2 This circuit is an npn-transistor input error amplifier that detects and amplifies the DC-DC converter output voltage, and inputs that signal to a PWM comparator. The 1.26 V internal reference voltage is applied to the noninverting input. Arbitrary gain and phase compensation can be set up by inserting a resistor and capacitor in series between the FB2 pin (pin 20) and the IN-2 pin (pin 19). The output voltage VOUT2 can be set using the circuit shown in the figure.
FB1 VOUT1 R1
22
21 IN-1 R2
Error amplifier 1 1.26 V To the PWM comparator input R1 + R2 R2
VOUT1 = 1.26 x
Figure 2. Connection method of error amplifier 1 (Step-up output) FB2 VOUT2 R1 Error amplifier 2 19 IN-2 R2 VOUT2 = 1.26 x 1.26 V To the PWN comparator input R1 + R2 R2
20
Figure 3. Connection method of error amplifier 2 (Step-up output)
14
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AN8049FHN
I Application Notes (continued)
[4] Function descriptions (continued) 5. Error amplifier 3 This circuit is a pnp-transistor input error amplifier that detects and amplifies the DC-DC converter output voltage and inputs that signal to a PWM comparator. Arbitrary gain and phase compensation can be set up by inserting a resistor and capacitor in series between the FB3 pin (pin 18) and the IN-3 pin (pin 17). The output voltage VOUT3 can be set using the circuit shown in the figure. Step-down output FB3 18 VREF VOUT3 R1 R3
IN+3 IN-3
Inverting output FB3 18 VREF
Error amplifier 3
16 17
R1
IN+3
Error amplifier 3
16 17
R2
R4
To the PWM comparator input
R2 VOUT3
IN-3
To the PWM comparator input R2 R1
VOUT3 =
RR R2 x 3 + 4 x VREF R4 R1 + R2
VOUT3 = -VREF x
Figure 4. Connection method of error amplifier 3 6. Timer latch short-circuit protection circuit This circuit protects the external main switching elements, flywheel diodes, choke coils, and other components against degradation or destruction if an excessive load or a short circuit of the power supply output continues for longer than a certain fixed period. The timer latch short-circuit protection circuit detects the output of the error amplifiers. If the DC-DC converter output voltage drops and an FB pin (pins 18, 20, or 22) voltage exceeds 0.9 V, the S.C.P. comparator outputs a low level and the timer circuit starts. This starts charging the external protection circuit delay time capacitor. If the error amplifier output does not return to the normal voltage range before that capacitor reaches 1.26 V, the latch circuit latches, the output drive transistors are turned off, and the dead-time is set to 100%. 7. Low input voltage malfunction prevention circuit (U.V.L.O.) This circuit protects the system against degradation or destruction due to incorrect control operation when the power supply voltage falls during power on or power off. The low input voltage malfunction prevention circuit detects the internal reference voltage that changes with the supply voltage level. While the supply voltage is rising, this circuit cuts off the output drive transistor until the reference voltage reaches 1.67 V. It also sets the dead-time to 100% and at the same time holds the S.C.P. pin (pin 23) and the DT pins (pins 1, 2, and 24) at 0 V, and the OSC pin (pin 15) at about 1.2 V. 8. PWM comparators The PWM comparators control the on-period of the output pulse according to their input voltage. The output transistors are turned on during periods when the OSC pin (pin 15) triangular wave is lower than both of the corresponding FB pin (pins 18, 20, or 22) and the corresponding DT pin (pins 1, 2, or 24). The PWM 2 circuit turns the output transistor on during periods when OSC pin (pin 15) triangular wave is at a higher level than both of the FB2 pin (pin 20) and the DT2 pin (pin 1). The maximum duty is set to 86% internally, but it can be set to a value lower than 86% by inserting a resistor between the corresponding DT pin and ground, and can be set to a value higher than 86% by inserting a resistor between the corresponding DT pin and the VREF pin. The IC's soft start function operates to gradually increase the width of the output pulse on-period during startup if a capacitor is inserted between the DT pin and ground.
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I Application Notes (continued)
[4] Function descriptions (continued) 9. Output 1 and output 2 blocks These output circuits have a totem pole structure. A constant-current source output with good line regulation can be set up freely by connecting current setting resistors to the RB pins. These circuits can provide a constant-current source output of up to 50 mA. 10. Output 3 block This output circuit has an open collector structure. An output current of up to 50 mA can be provided, and the output pin has a breakdown voltage of 15 V. 11. CTL block The CTL block output circuit also has a totem pole structure. A constant-current source output with good line regulation can be set up freely by connecting current setting resistors to the RB2 pin. The CTL block can provide a constant-current source output of up to 50 mA. [5] Time constant setup for the timer latch short-circuit protection circuit Figure 6 shows the structure of the timer latch short-circuit protection circuit. The short-circuit protection comparator continuously compares a 0.9 V reference voltage with the FB1, FB2, and FB3 error amplifier outputs. When the DC-DC converter output load conditions are stable, the short-circuit protection comparator holds its average value since there are no fluctuations in the error amplifier outputs. At this time, the output transistor Q1 will be in the conducting state, and the S.C.P. pin will be held at 0 V. If the output load conditions change rapidly and a high-level signal (0.9 V or higher) is input to the short-circuit protection comparator from the error amplifier output, the short-circuit protection comparator will output a low level and the output transistor Q1 will shut off. Then, the capacitor CSCP connected to the S.C.P. pin will start to charge. When the external capacitor CSCP is charged to about 1.26 V by the constant current of about 1.1 mA, the latch circuit will latch and the dead-time will be set to 100% with the output held fixed at the low level. Once the latch circuit has latched, the S.C.P. pin capacitor will be discharged to about 0 V, but the latch circuit will not reset unless either power is turned off or the power supply is restarted using on/off control. VSCP (V) tPE 1.26 V = ICHG x CSCP Short-circuit detection time tPE 1.26 tPE (s) = 1.15 x CSCP (F) At power supply startup, the output appears to be in the shorted state, and the IC starts to charge the S.C.P. pin capacitor. Therefore, users must select an external capacitor that allows the DC-DC converter output voltage to rise before the latch circuit in the later stage latches. In particular, care is required if the soft start function is used, since that function makes the startup time longer. On/off control VCC FB1 FB2 FB3 22 20 18 S.C.P. comp. Q1 1.1 A U.V.L.O. Latch R Q S High level detection comparator 1.26 V
0 t (s) Figure 5. S.C.P. pin charging waveform
VREF
Output shutoff
0.9 V 23 S.C.P. Figure 6. Short-circuit protection circuit
16
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AN8049FHN
I Application Notes (continued)
[6] Parallel synchronous operation of multiple ICs Multiple instances of this IC can be operated in parallel. If the OSC pins (pin 15) and Off pins (pin 6) are connected to each other as shown in figure 7, the ICs will operate at the same frequency. It is also possible to operate a one-channel control IC (e.g. the AN8016SH or AN8016NSH) and a two-channel control IC (e.g. the AN8017SA or AN8018SA) in this parallel synchronous mode. In this case, short the OSC and Off pins together. Note that it is not possible to control the on/off states of each IC operating in this mode independently. It is only possible to turn all the ICs on or off at the same time remotely.
OSC pins connected together
15 OSC
AN8049FHN
AN8049FHN S.C.P. 23
S.C.P. 23
Off 6
VREF 7
15 Off 6
Off pins connected together
OSC VREF 7
H L
Figure 7. Slave operation circuit example
SDH00011BEB
17
AN8049FHN
I Application Notes (continued)
[7] Sequential operation Delays can be provided in the startup times by inserting capacitors (CCTL) between the CTL pins and ground. Delay time: tDLY = 1.26 (V) x CCTL (F)/1.1 (A) (s) Note that the individual channels can also be turned on or off independently by external signals. These external signals may have voltages in the range 0 V to VCC. CTL1 CTL2 CTL3
1.26 V AN8049FHN U.V.L.O. cleared
CTL3 3
CTL2 4
CTL1 5
CCTL3 CCTL2
CCTL1
OUT1
OUT2 CCTL1 < CCTL2 < CCTL3 OUT3 Figure 8. Sequential operation
18
SDH000011BEB
AN8049FHN
I Application Notes (continued)
[8] Differences between this IC and the AN8049SH The pin arrangements differ. The AN8049SH is an alternative package version of this IC.
AN8049FHN
VCC 14 OUT3 13 IN-2 IN-3 IN+3 16 OSC 15 FB3 18
19
17
FB2 IN-1 FB1 S.C.P. DT3
20 21 22 23 24
12 11 10 9 8
GND OUT2 OUT1 RB1 RB2
1
2
3
4
5
6 Off
CTL3
CTL2
CTL1
AN8049SH
OUT3 OUT2 OUT1 12 13 GND RB1 11 14 IN-1 IN-2 IN-3 IN+3 OSC 17 VCC 16 VREF 9 FB1 FB2 FB3
24
23
22
21
20
19
18
CTL1
S.C.P.
DT3
DT2
DT1
CTL3
CTL2
Off
RB2
10
1
2
3
4
5
6
7
8
15
VREF
DT2
DT1
7
SDH00011BEB
19
AN8049FHN
I Application Notes (continued)
[9] Error amplifier frequency characteristics 1. Error amplifiers 1 and 2 (Test circuit)
10 F VIN 4 mV[p-p] 2.3 V 1 k
Gain (dB) Phase ()
100 k
40 30
IN-1 100 k
Amp.1
VOUT FB1
20 10 0 -10 -20 180 135
VREF 1.26 V
90
45
0
-45 1k
10k
100k
1M
10M
100M
Frequency (Hz)
2. Error amplifier 3 (Test circuit)
1V 10 F VIN 4 mV[p-p] 1 k IN-3
Amp.3 40 30
1 kW IN+3 1 k
Gain (dB) Phase ()
FB3 VOUT
20 10 0 -10 -20 0 -45 -90 -135 -180 -225 1k
100 k 10 F
10k
100k
1M
10M
100M
Frequency (Hz)
20
SDH000011BEB
AN8049FHN
I Application Circuit Example
VIN
Q3
- VO3
13 OUT3
19 IN-2
17 IN-3
16 IN+3
15 OSC
14 VCC
18 FB3
VREF + VO2 Q2
FB2 20 IN-1 21 FB1 22 S.C.P. 23 DT3 24
12 GND 11 OUT2 10 OUT1 9 8 RB1 RB2
+ VO1 Q1
DT2 1
DT1 2
CTL3 3
CTL2 4
CTL1 5
Off 6
VREF 7
SDH00011BEB
21
AN8049FHN
I Evaluation Board
1. The element numbers of the board pair with the ones of the circuit. 2. "JP" of the board shows the jumper. Short circuit. * Circuit
Input VIN 3V7V
RC3 10 k
Input filter (When no using, short circuit the both ends of RIN1)
1 000 pF CC2 RC4 RC5 10 k 1 k LC1
QC1
QC2 DC1 CC3 10 F
CC4 RC1 Inverting 0.47 F 100 k
VOUT3 -10 V
CC1 1 000 pF RC2 13 k
680 pF
RIN1
CIN1 1 F
1 000 pF
C20 1 000 pF
LB1 100 H DB1 QB1 CB2 10 F CB3 0.47 F LA1 47 H
15 OSC 3 k
18 FB3 C18
R15
CIN2
C15
CB1 0.012 F
VREF Step-up VOUT2 +10 V
RB1 910 k RB2 130 k
FB2 20
C22 1 000 pF
14 VCC
R20 1 M
13 OUT3
19 IN-2
17 IN-3
16 IN+3
12 GND 11 OUT2 10 OUT1 9 RB1 8 RB2
QA1 DA1 CA2 33 F
IN-1 21
1 M
FB1 22
R22 0.012 F S.C.P. 23 C23
CA1 RA1 640 k CA3 0.47 F RA2 130 k
Step-up VOUT1 +7.5 V
DT3 24
DT2 1 DT1 2 CTL3 3 CTL2 4 CTL1 5 Off 6 VREF 7
C24 0.012 F
0.012 F
0.012 F
C7
R8 3 k
R9 1 k
0.1 F
C1
C2
C3
C4
* Board
C5
GND
On/Off
LC1 DC1
CIN1 CC2 RC3 RC4 JP CIN2
RIN1 C15 R15
OUT3
VIN
CC1 RC1
JP
JP
GND
QC1 QC2 CC4
OUT2
CC3 JP GND
RC5 DB1 LB1 JP CB3 CB2 DA1
OUT1
RC2 C18 RB2 JP R20 C20 QB1 RB1 CB1 RA1 CA1
On/Off
8049
R22 RA2 C22
LA1 QA1
JP
CA3 CA2 R9 R8 C7 C5 C4 C3 C2 C1 C24 C23
AN8049FHN
22
SDH000011BEB
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2001 MAR

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